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@Minchan-Kwon Minchan-Kwon commented Nov 30, 2025

Fixed Verilog syntax errors for the benchmark suite to run.

Summary by CodeRabbit

  • Bug Fixes

    • Corrected multiple syntax issues and an internal signal type to ensure generated designs compile and synthesize reliably.
    • Updated a clock reference used during instantiation for consistent hardware generation.
  • New Features

    • Added two new generated modules for additional clock/test scenarios.
  • Chores

    • Improved SDC generation tooling: more deterministic selections, stricter option validation, revised create_clock output formatting, and cleaner command assembly.

✏️ Tip: You can customize this high-level summary in your review settings.

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coderabbitai bot commented Nov 30, 2025

Walkthrough

Small Verilog netlist fixes and additions (semicolon corrections, internal signal type change, one module instantiation swapped), two new netlist modules added, and a substantial refactor of the SDC generation script (option validation, selector syntax, and command assembly).

Changes

Cohort / File(s) Change Summary
Semicolon / syntax fixes
auto_generated/netlist_files/set_false_path_netlist.v, auto_generated/netlist_files/set_max_delay_netlist.v, auto_generated/netlist_files/set_min_delay_netlist.v, auto_generated/netlist_files/set_multicycle_path_netlist.v
Added missing trailing semicolons to non-blocking assignments inside always blocks; no behavioral changes.
Signal type & cleanup
auto_generated/netlist_files/set_clock_uncertainty_netlist.v
Changed internal data_internal from wire to reg to match assignment inside an always block; removed a redundant always block.
Module instantiation change
auto_generated/netlist_files/set_output_delay_netlist.v
Replaced instantiation module FF with FF_ref for the ff_ref instance; wiring/logic otherwise unchanged.
New netlist modules
auto_generated/netlist_files/all_clocks_netlist.v, auto_generated/netlist_files/set_disable_timing_netlist.v
Added all_clocks (inputs clk1, clk2, D; output reg Q; clk2 unused) and set_disable_timing (module now declares clk1, D, Q and assigns Q on posedge clk1) netlists.
SDC generator overhaul
scripts/generate_sdc.py
Extensive refactor: changed default PERIODS/PINS, switched many selectors to [get_*] syntax, tightened mutual-exclusion/validation for options, made deterministic pin/clock selection, adjusted waveform timing ordering, and changed generator command assembly and return shapes (e.g., create_clock prerequisites added).

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~45 minutes

  • Focus review on scripts/generate_sdc.py: option mutual-exclusion, selector/[get_*] correctness, and the altered generator outputs (ensure callers/consumers accept new command shapes).
  • Verify new netlist modules for declared/used signals (e.g., all_clocks clk2 unused; set_disable_timing declares clk1 in this diff).
  • Confirm FFFF_ref instantiation matches available module definitions.
  • Quick pass on semicolon fixes in netlists (low risk).

Poem

🐇 I hopped through netlists, tail a-fluff,
Semicolons settled — not one too rough.
A wire became reg, a clock found place,
Scripts rearranged with tidy grace.
Happy hops — SDCs embrace! ✨

Pre-merge checks and finishing touches

✅ Passed checks (3 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title check ✅ Passed The title accurately reflects the primary focus of the changeset: fixing Verilog syntax errors across multiple netlist files and related script adjustments.
Docstring Coverage ✅ Passed Docstring coverage is 92.86% which is sufficient. The required threshold is 80.00%.
✨ Finishing touches
  • 📝 Generate docstrings
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Post copyable unit tests in a comment

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Actionable comments posted: 1

📜 Review details

Configuration used: CodeRabbit UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between aa0e6bb and 6c82768.

📒 Files selected for processing (6)
  • auto_generated/netlist_files/set_clock_uncertainty_netlist.v (2 hunks)
  • auto_generated/netlist_files/set_false_path_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_max_delay_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_min_delay_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_multicycle_path_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_output_delay_netlist.v (1 hunks)
🔇 Additional comments (6)
auto_generated/netlist_files/set_max_delay_netlist.v (1)

48-51: LGTM!

The missing semicolons have been correctly added to terminate the non-blocking assignments in the always block. This is a necessary Verilog syntax fix.

auto_generated/netlist_files/set_multicycle_path_netlist.v (1)

48-51: LGTM!

Correct syntax fix - semicolons added to terminate the procedural assignments.

auto_generated/netlist_files/set_false_path_netlist.v (1)

48-51: LGTM!

Correct syntax fix - semicolons properly terminate the non-blocking assignments in the always block.

auto_generated/netlist_files/set_min_delay_netlist.v (1)

48-51: LGTM!

Correct syntax fix - semicolons added to terminate the procedural assignments.

auto_generated/netlist_files/set_output_delay_netlist.v (1)

21-21: LGTM!

The instantiation now correctly references module FF_ref (defined at line 38) instead of the non-existent FF. This fix resolves the module elaboration error while maintaining all port connections.

auto_generated/netlist_files/set_clock_uncertainty_netlist.v (1)

22-22: Correct fix: wire to reg conversion.

The change from wire to reg is necessary because data_internal is assigned inside an always block (line 25). This is a required syntax correction.

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Actionable comments posted: 5

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)
scripts/generate_sdc.py (1)

682-710: Bug: to_obj uses through_list instead of to_list.

to_list is defined on line 684 but never used. On line 710, to_obj is assigned from through_list instead of to_list. This appears to be a copy-paste error that affects the correctness of generated -to options.

-            to_obj = random.choice(through_list)
+            to_obj = random.choice(to_list)
🧹 Nitpick comments (1)
scripts/generate_sdc.py (1)

426-432: Remove extraneous f prefix from strings without placeholders.

These f-strings have no placeholders and don't need the f prefix:

  • Line 426: f"-clock [get_clocks src_clk]""-clock [get_clocks src_clk]"
  • Line 432: f"-reference_pin [get_pins ff_ref/clk]""-reference_pin [get_pins ff_ref/clk]"

This pattern repeats in multiple places (lines 496, 503, 567, 630, 634, 638, 642, 646, 650, 1200, 1204).

📜 Review details

Configuration used: CodeRabbit UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 6c82768 and 0e603cf.

📒 Files selected for processing (4)
  • auto_generated/netlist_files/all_clocks_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_clock_uncertainty_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_disable_timing_netlist.v (1 hunks)
  • scripts/generate_sdc.py (23 hunks)
🧰 Additional context used
🪛 Ruff (0.14.6)
scripts/generate_sdc.py

220-220: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


221-221: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


229-229: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


426-426: f-string without any placeholders

Remove extraneous f prefix

(F541)


432-432: f-string without any placeholders

Remove extraneous f prefix

(F541)


443-443: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


496-496: f-string without any placeholders

Remove extraneous f prefix

(F541)


503-503: f-string without any placeholders

Remove extraneous f prefix

(F541)


514-514: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


546-546: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


550-550: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


567-567: f-string without any placeholders

Remove extraneous f prefix

(F541)


630-630: f-string without any placeholders

Remove extraneous f prefix

(F541)


634-634: f-string without any placeholders

Remove extraneous f prefix

(F541)


638-638: f-string without any placeholders

Remove extraneous f prefix

(F541)


642-642: f-string without any placeholders

Remove extraneous f prefix

(F541)


646-646: f-string without any placeholders

Remove extraneous f prefix

(F541)


650-650: f-string without any placeholders

Remove extraneous f prefix

(F541)


684-684: Local variable to_list is assigned to but never used

Remove assignment to unused variable to_list

(F841)


778-778: Local variable to_list is assigned to but never used

Remove assignment to unused variable to_list

(F841)


798-798: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


802-802: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


803-803: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


804-804: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


872-872: Local variable to_list is assigned to but never used

Remove assignment to unused variable to_list

(F841)


893-893: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


897-897: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


898-898: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


899-899: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


966-966: Local variable to_list is assigned to but never used

Remove assignment to unused variable to_list

(F841)


972-972: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


994-994: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


995-995: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


996-996: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


1196-1196: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


1200-1200: f-string without any placeholders

Remove extraneous f prefix

(F541)


1204-1204: f-string without any placeholders

Remove extraneous f prefix

(F541)

🔇 Additional comments (4)
auto_generated/netlist_files/set_clock_uncertainty_netlist.v (1)

22-22: Correct fix: data_internal must be reg for procedural assignment.

The change from wire to reg is necessary since data_internal is assigned inside an always block (line 25). The removal of the redundant always block (mentioned in the summary) also resolves the prior multi-driver concern.

scripts/generate_sdc.py (3)

591-612: Good addition of mutual exclusion validation.

The new logic properly enforces mutual exclusivity constraints:

  • Only one -from variant allowed
  • Only one -to variant allowed
  • Both from and to must be present together (or neither)
  • objects cannot be combined with from options

1179-1187: Good addition of exclusive options validation.

The new logic correctly enforces that -divide_by, -multiply_by, and -edges are mutually exclusive, which aligns with SDC specification.


1373-1384: Good addition of mutual exclusion validation for all_registers.

The logic correctly enforces that return type options (-cells, -data_pins, -clock_pins, -async_pins, -output_pins) are mutually exclusive, and that -level_sensitive and -edge_triggered cannot be combined.

Comment on lines 10 to 15
module all_clocks(
input wire clk1,
input wire clk2,
input wire D,
output reg Q,
);
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⚠️ Potential issue | 🔴 Critical

Syntax error: Trailing comma in port list.

The trailing comma after output reg Q, on line 15 will cause a Verilog compilation error. Also note that clk2 is declared but unused in the module logic (this may be intentional for SDC testing purposes).

 module all_clocks(
     input wire clk1,
     input wire clk2,
     input wire D,
-    output reg Q,
+    output reg Q
 );
📝 Committable suggestion

‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.

Suggested change
module all_clocks(
input wire clk1,
input wire clk2,
input wire D,
output reg Q,
);
module all_clocks(
input wire clk1,
input wire clk2,
input wire D,
output reg Q
);
🤖 Prompt for AI Agents
In auto_generated/netlist_files/all_clocks_netlist.v around lines 10 to 15,
remove the trailing comma after "output reg Q," in the module port list to fix
the Verilog syntax error; additionally, either remove the declared but unused
"clk2" port if it's not needed, or document/annotate its intentional unused
status (or wire it into the design) to avoid lint/compile warnings.

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Actionable comments posted: 0

♻️ Duplicate comments (2)
scripts/generate_sdc.py (2)

668-763: set_false_path: to_obj bug fixed and exclusivity constraints added

This now correctly selects to_obj from to_list (rather than through_list as previously flagged) and enforces at most one from*, through*, and to* variant per command, which matches the intended semantics for mutually exclusive variants.


858-951: set_min_delay mirrors set_max_delay logic correctly

The structure and mutual exclusion checks are consistent with set_max_delay, and to_obj is now chosen from to_list as intended. This keeps the min/max delay generators in sync and fixes the earlier to_obj selection issue.

🧹 Nitpick comments (6)
scripts/generate_sdc.py (6)

455-524: set_output_delay option guards mirror input-delay behavior appropriately

The same mutual-exclusion rules as set_input_delay are now applied here, and the fixed -clock [get_clocks src_clk] / -reference_pin [get_pins ff_ref/clk] choices are coherent with the clock and FF naming used elsewhere. One tiny nit: clk = random.choice(CLOCKS) is now unused and can be dropped as dead code if you want to keep linters quiet later.


526-577: Consider making set_clock_latency syntax closer to canonical SDC

Spec examples typically use set_clock_latency -source <latency> [get_clocks {clk}], i.e., options first, then latency, then clocks. (mithro-vtr.readthedocs.io)
Your generator currently emits set_clock_latency <delay> <object> [-source] ..., which may still parse on tolerant engines but is non‑canonical and could be less portable across SDC implementations.

If you care about portability, I’d suggest reordering to something like:

pieces = ["set_clock_latency"]
if "-source" in option_combination:
    pieces.append("-source")
# other flags...
pieces.append(str(delay))
pieces.append(random.choice(CLOCKS))  # or CLOCKS+PINS+PORTS for the target list

Please confirm against your target STA engine (e.g., OpenSTA/TimeQuest/VPR) whether the current ordering is accepted, and adjust if needed.


579-667: New mutual-exclusion logic in set_clock_uncertainty is a good step; consider tightening object rules

The from_options/to_options counting avoids mixing multiple from/to variants and prevents “half-specified” from/to (only one side set), which aligns with typical clock‑to‑clock uncertainty usage. (mithro-vtr.readthedocs.io)

Given you already block objects when any -from* is present, you may want to also block objects when any -to* is present for symmetry, unless you explicitly rely on set_clock_uncertainty -to ... <uncertainty> [objects] forms. That would look like:

if "objects" in option_combination and (from_count > 0 or to_count > 0):
    continue

764-856: set_max_delay mutual-exclusion logic is solid; option semantics could be tightened further

The new from_options/through_options/to_options counting ensures only one variant from each family is present, which prevents invalid mixes like -from + -rise_from. That’s a clear improvement.

The docstring says -rise/-fall “can only be used with plain -to, -from, -through.” Right now, combinations like -rise with -rise_from are still possible. If your target STA treats those as illegal or ambiguous, you might want an extra guard that skips any combination where -rise/-fall co‑occurs with -rise_*/-fall_* variants.


953-1054: set_multicycle_path: exclusivity checks look good; review multiplier placement and option conflicts

The new from_options/through_options/to_options mutual-exclusion logic, plus the -start/-end conflict check, is a nice improvement and avoids many invalid combinations.

Two things to double‑check:

  1. multiplier is chosen once per generate_set_multicycle_path() call, so every emitted command in that run shares the same multicycle factor. If you intended to vary multipliers per combination, move the multiplier = random.choice(DIVISORS) inside the inner loop.
  2. The docstring says -setup/-hold and -rise/-fall are mutually exclusive, but the current logic doesn’t enforce that. If your STA tool is strict about those being alternatives, you may want to skip combinations containing both flags.

1511-1517: Narrowed default command_list to path-based generators

Commenting out the broad command_list and using ["set_false_path", "set_min_delay", "set_max_delay", "set_multicycle_path"] by default is reasonable given the new netlist focus. Just be aware that other generators (e.g., create_clock, set_clock_uncertainty) are still wired into GENERATORS; if you later want coverage for them, you’ll need to re-expand command_list in your driver script or here.

📜 Review details

Configuration used: CodeRabbit UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 0e603cf and 3f5aeaf.

📒 Files selected for processing (3)
  • auto_generated/netlist_files/all_clocks_netlist.v (1 hunks)
  • auto_generated/netlist_files/set_disable_timing_netlist.v (1 hunks)
  • scripts/generate_sdc.py (23 hunks)
🚧 Files skipped from review as they are similar to previous changes (2)
  • auto_generated/netlist_files/all_clocks_netlist.v
  • auto_generated/netlist_files/set_disable_timing_netlist.v
🧰 Additional context used
🪛 Ruff (0.14.6)
scripts/generate_sdc.py

220-220: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


221-221: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


229-229: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


426-426: f-string without any placeholders

Remove extraneous f prefix

(F541)


432-432: f-string without any placeholders

Remove extraneous f prefix

(F541)


443-443: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


496-496: f-string without any placeholders

Remove extraneous f prefix

(F541)


503-503: f-string without any placeholders

Remove extraneous f prefix

(F541)


514-514: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


546-546: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


550-550: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


567-567: f-string without any placeholders

Remove extraneous f prefix

(F541)


630-630: f-string without any placeholders

Remove extraneous f prefix

(F541)


634-634: f-string without any placeholders

Remove extraneous f prefix

(F541)


638-638: f-string without any placeholders

Remove extraneous f prefix

(F541)


642-642: f-string without any placeholders

Remove extraneous f prefix

(F541)


646-646: f-string without any placeholders

Remove extraneous f prefix

(F541)


650-650: f-string without any placeholders

Remove extraneous f prefix

(F541)


708-708: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


709-709: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


710-710: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


798-798: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


802-802: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


803-803: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


804-804: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


893-893: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


897-897: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


898-898: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


899-899: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


972-972: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


994-994: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


995-995: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


996-996: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


1196-1196: Standard pseudo-random generators are not suitable for cryptographic purposes

(S311)


1200-1200: f-string without any placeholders

Remove extraneous f prefix

(F541)


1204-1204: f-string without any placeholders

Remove extraneous f prefix

(F541)

🔇 Additional comments (6)
scripts/generate_sdc.py (6)

24-32: Updated PERIODS/PINS/PORTS/CLOCKS constants look consistent with get_ usage*

The new value ranges and explicit [get_* …] forms align with how the generators build SDC commands and with the updated netlists; no issues from a generation/coverage perspective.


198-234: generate_create_clock changes look good

Using {5, 10, 20} for PERIODS, random but bounded rise_time/fall_time, and explicit pin forms in pin_list all produce plausible create_clock calls and remain structurally valid. No further changes needed here.


385-454: Stronger validation for set_input_delay combinations is correct

The new guards (requiring -clock when -clock_fall is present, making -max/-min mutually exclusive, and disallowing -reference_pin together with latency options) match common SDC expectations and avoid obviously invalid combinations. The fixed -clock and -reference_pin object choices also look consistent with the new netlists.


1173-1242: create_generated_clock: exclusive options and pin selection look consistent

Limiting -divide_by/-multiply_by/-edges to at most one per command matches SDC expectations, and using [get_pins reg0/clk] plus a -source pointing to either a port or MMCM input produces realistic generated-clock scenarios. The added create_clock prerequisite for src_clk is also consistent with the rest of the script.


1306-1307: all_clocks now emits prerequisite create_clock calls explicitly

Returning a single multi-line string with two create_clock definitions followed by all_clocks matches the updated netlists and ensures the clocks exist before all_clocks is referenced. This is a sensible change.


1366-1407: all_registers: new exclusivity checks match the documented intent

The return_type_options counting correctly enforces that only one of -cells/-data_pins/-clock_pins/-async_pins/-output_pins is present, and the additional guard preventing simultaneous -level_sensitive and -edge_triggered flags matches the docstring. This should prevent a lot of invalid SDC from being generated.

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LGTM

@AlexandreSinger AlexandreSinger merged commit 8d43039 into siliconcompiler:master Dec 2, 2025
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