[Docs] Added Image Description of Benchmark Suite #24
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WalkthroughAdds three auto-generated Verilog netlist modules (get_clocks, get_pins, get_ports) and refactors the SDC-generation script (scripts/generate_sdc.py) to always append patterns and prefix generated commands with create_clock prerequisites. Changes
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~20 minutes
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✨ Finishing touches🧪 Generate unit tests (beta)
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Actionable comments posted: 4
🧹 Nitpick comments (1)
auto_generated/netlist_files/get_pins_netlist.v (1)
1-35: Verify file completeness.The file appears to be missing a final newline at the end. While not a critical issue, it's a common best practice to end source files with a newline character.
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auto_generated/netlist_files/get_clocks_netlist.v(1 hunks)auto_generated/netlist_files/get_pins_netlist.v(1 hunks)auto_generated/netlist_files/get_ports_netlist.v(1 hunks)
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Actionable comments posted: 1
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⚠️ Outside diff range comments (1)
scripts/generate_sdc.py (1)
314-352:generate_get_pins: you’re iterating unused options → duplicate outputs and wasted generationAfter the change, only
-regexp/-nocase/-quietare actually appended, but the loop still enumerates combinations over["-hierarchical", "-hsc", "-filter", ...](Line 321). That will generate many identical commands and file duplicates. Tightenoptional_options(and update the docstring) to match what’s emitted.def generate_get_pins(): ''' - Required: - Optional: -hierarchical, -hsc, -filter, -regexp, -nocase(Valid only with -regexp), -quiet, -of_objects, patterns - Note: -hierarchical cannot be used with -of_objects + Optional: -regexp, -nocase (legal only with -regexp), -quiet ''' commands = [] #List containing all possible combinations of options - optional_options = ["-hierarchical", "-hsc", "-filter", "-regexp", "-nocase", "-quiet", "-of_objects", "patterns"] + optional_options = ["-regexp", "-nocase", "-quiet"]
🧹 Nitpick comments (2)
scripts/generate_sdc.py (2)
236-273:generate_get_ports: consider dropping the create_clock prerequisite and/or align pattern to-regexp
get_portsgenerally doesn’t require clocks to exist; prefixingcreate_clockmay be harmless but can add noise and (if the referenced port doesn’t exist) introduce avoidable tool errors in suites that only want to validateget_ports. Also, if-regexpis present, ensurepatternis a regex (not a glob-ish token like*in).- #Add create_clock prerequisites - pieces = ("create_clock -period 10 -name clk [get_ports clk]\n" + pieces) + # If you truly need prerequisites here, consider referencing a port that always exists + # in the benchmark netlist, or omit prerequisites for get_ports entirely. + # pieces = ("create_clock -period 10 -name clk [get_ports clk]\n" + pieces)- pattern = generate_pattern("port") + pattern = generate_pattern("port") # consider generate_pattern("port_regex") when -regexp is set pieces.append(pattern)
274-313:generate_get_clocks: prereq clocks should be conditional on the chosen clock patternYou always create 4 clocks (clk1/clk2/clk_gen/clock) even if the generated
get_clockspattern targets something else; this can create unnecessary constraints and failures if some ports don’t exist in a given netlist. Consider emitting prerequisites only for the clocks implied by the pattern (or ensure the netlists always define these ports).
| "clock": ["clk*", "clk_gen", "clock", "clk1"], | ||
| "port": ["data*", "*in", "*out", "valid_in"], | ||
| "pin": ["u1/*", "*/Q", "u2/D", "*/clk"], | ||
| "cell": ["inst*", "reg_*", "*_buffer"], | ||
| "net": ["net*", "n[0-9]*", "*_data"] | ||
| } |
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Ensure patterns match the selected mode (glob vs -regexp)
PATTERNS now feeds both plain mode and -regexp mode. Several entries (e.g., clk*, *in, */Q) look like glob patterns; under -regexp they may be invalid or at least semantically different than intended depending on the SDC implementation. Consider maintaining separate pattern banks (glob vs regex) or translating when -regexp is present.
PATTERNS = {
- "clock": ["clk*", "clk_gen", "clock", "clk1"],
- "port": ["data*", "*in", "*out", "valid_in"],
- "pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
+ # Consider splitting into "glob" vs "regex" banks if -regexp is used.
+ "clock": ["clk*", "clk_gen", "clock", "clk1"],
+ "port": ["data*", "*in", "*out", "valid_in"],
+ "pin": ["u1/*", "*/Q", "u2/D", "*/clk"],
"cell": ["inst*", "reg_*", "*_buffer"],
"net": ["net*", "n[0-9]*", "*_data"]
}📝 Committable suggestion
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Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.
| "clock": ["clk*", "clk_gen", "clock", "clk1"], | |
| "port": ["data*", "*in", "*out", "valid_in"], | |
| "pin": ["u1/*", "*/Q", "u2/D", "*/clk"], | |
| "cell": ["inst*", "reg_*", "*_buffer"], | |
| "net": ["net*", "n[0-9]*", "*_data"] | |
| } | |
| PATTERNS = { | |
| # Consider splitting into "glob" vs "regex" banks if -regexp is used. | |
| "clock": ["clk*", "clk_gen", "clock", "clk1"], | |
| "port": ["data*", "*in", "*out", "valid_in"], | |
| "pin": ["u1/*", "*/Q", "u2/D", "*/clk"], | |
| "cell": ["inst*", "reg_*", "*_buffer"], | |
| "net": ["net*", "n[0-9]*", "*_data"] | |
| } |
🤖 Prompt for AI Agents
In scripts/generate_sdc.py around lines 103 to 108, PATTERNS currently contains
glob-style entries that are being used regardless of whether the SDC engine is
invoked in plain (glob) or -regexp mode; this can produce incorrect or invalid
matches. Fix by branching on the selected mode: if mode == "regexp" either (a)
maintain a separate PATTERNS_REGEXP mapping with proper regular expressions for
each key, or (b) programmatically translate glob patterns to equivalent regex
(escaping as needed and converting * -> .* and ? -> .) before emitting them;
validate converted patterns (e.g., compile them) and use the appropriate bank
when generating the SDC output.
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Added the images describing the benchmark suite
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